Mentor Graphics Modelsim Se-64 10.7 |best|

It supports behavioral, RTL, and gate-level code simulation. This includes support for VHDL VITAL and Verilog gate libraries, with timing provided via the Standard Delay Format (SDF).

This award-winning architecture allows for the transparent mixing of VHDL and Verilog within a single design. Mentor Graphics ModelSim SE-64 10.7

is the 64-bit Standard Edition released in the 10.7 product cycle. It is designed for professional teams verifying complex FPGAs (Xilinx, Intel/Altera) or custom ASICs. It supports behavioral, RTL, and gate-level code simulation