Week 1: Lecture + intro to tools Week 2: Fixed-point modeling & FIR design assignment Week 3: Lab: FIR implementation (RTL/HLS) Week 4: FFT theory + IP lab Week 5: Integrate pipeline + testbench Week 6: Hardware bring-up + optimization Week 7: Final report + demos Week 8: Advanced topics / student presentations
. This allows them to handle high-bandwidth applications—such as digital communications and video processing—with lower power consumption and higher throughput than multi-processor systems. Xilinx University Program Product Brief Xilinx University Program - DSP for FPGA Primer...
The primer explicitly compares HLS versus RTL approaches, noting that while HLS accelerates design, RTL provides ultimate control. Week 1: Lecture + intro to tools Week
Connect theoretically derived designs with real-world FPGA performance limits. Resource Optimization: noting that while HLS accelerates design